1. Field of the Invention
This invention relates to a keyed clamp circuit that performs clamping to a video signal, especially to a keyed clamp circuit that can accurately clamp a video signal with an equalizing pulse and a vertical synchronization signal.
2. Description of the Related Art
The edge level of a horizontal synchronization signal needs to be kept at a certain level in an analog video signal. A clamp circuit can be used as a circuit for equalizing the edge level of the horizontal synchronization signal of a video signal. A keyed clamp circuit is a type of the clamp circuit.
A sync tip clamp of the keyed clamp circuit equalizes the edge level of the horizontal synchronization signal with a reference level while clamp pulses are coming, equalizing the direct current level at the edge of the horizontal synchronization signal. The clamp pulse is generated during the horizontal synchronization signal period. When there is a difference in the direct current level between the reference level and the direct current level at the edge of the horizontal synchronization signal during the clamp pulse period, the difference is detected and a capacitor is charged by the voltage difference. The video signal is superimposed on the voltage of the capacitor. Therefore, the edge level of the horizontal synchronization signal of the video signal is equalized.
FIG. 2 is a block diagram of the keyed clamp circuit. An input terminal 1 in FIG. 2 receives the video signal shown in FIGS. 3A and 3B. FIG. 3A shows a composite video signal, which includes a vertical synchronization signal, the horizontal synchronization signal, an equalizing pulse, and a brilliant signal. The video signal from the input terminal 1 is then applied to a synchronization signal separation circuit 4 after being clamped by the clamp circuit 2 and a capacitor 3 for stopping direct current.
The synchronization signal separation circuit 4 slices the composite video signal shown in FIG. 3A at the level shown as a dotted line in the figure. The synchronization signal separation circuit 4 also generates a vertical blanking pulse shown in FIG. 3B. The synchronization signal sliced at the level shown as the dotted line in FIG. 3A is then applied to a clamp pulse generation circuit 5. The clamp pulse generation circuit 5 applies the synchronization signal to the clamp circuit 2.
However, the clamp pulse generation circuit 5 does not apply the synchronization signal to the clamp circuit 2 during the entire period. The clamp pulse generation circuit 5 does not apply the synchronization signal to the clamp circuit 2 during a blanking pulse period when the blanking pulse shown in FIG. 3B is generated. Therefore, the clamp circuit 2 performs clamping during the period except the blanking pulse period. The clamped composite video signal is obtained at an output terminal 6 through this operation.
The reason why the clamp circuit 2 does not perform the clamping of the video signal during the blanking pulse period will be explained. FIG. 4A shows the horizontal synchronization signal, and FIG. 4B shows the clamp pulse generated from the horizontal synchronization signal in FIG. 4A by the keyed clamp circuit shown in FIG. 2. The level of the horizontal synchronization signal shown in FIG. 4A is detected during the T1 period shown in FIG. 4B. FIG. 4C shows the equalizing pulse. The pulse width and the cycle of the equalizing pulse are a half of those of the horizontal synchronization signal. Therefore, when the level of the equalizing pulse shown in FIG. 4C is detected during the T1 period shown in FIG. 4B, the edge level of the equalizing pulse can not be detected correctly, because the level during the T2 period shown in FIG. 4C will be also detected.
Therefore, the clamp circuit 2 does not perform clamping to the video signal during the blanking pulse period when the equalizing pulse is present.
However, if the clamping of the video signal is not performed during the blanking pulse period, the average direct current level becomes lower compared to the period when there is a brilliant signal, because there is no brilliant signal during the blanking pulse period. When this sort of signal goes through the capacitor 3 for stopping a direct current, a phenomenon called V-sag, where the average direct current level of the video signal goes up, will take place. Although the keyed clamp can absorb V-sag, V-sag can not be absorbed when the clamp pulse is stopped during the blanking pulse period.
Therefore, the clamp circuit that is capable of performing keyed clamping by generating the clamp pulse according to the equalizing pulse and the vertical synchronization signal even during the blanking pulse period is preferable.